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Disambiguation of "Yanagisawa, Masao"

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MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures.

, , , and . IEICE Electron. Express, 9 (17): 1414-1422 (2012)

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Masao Sekine

Masao Tanaka

Masao Watanabe

Mohamed Abdul-Jalil Ahmed Masaoud

Fidelis Taliwawa Masao

 

Other publications of authors with the same name

A delay variation and floorplan aware high-level synthesis algorithm with body biasing., , , and . ISQED, page 75-80. IEEE, (2016)State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit., , , and . APCCAS, page 607-610. IEEE, (2012)A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures., , , and . SoCC, page 7-12. IEEE, (2015)A robust scan-based side-channel attack method against HMAC-SHA-256 circuits., , and . ICCE-Berlin, page 79-84. IEEE, (2017)An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays., , , and . ASP-DAC, page 519-526. IEEE, (1998)Area/delay estimation for digital signal processor cores., , , , and . ASP-DAC, page 156-161. ACM, (2001)A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (12): 2398-2411 (2016)A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (11): 2439-2450 (2017)Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (12): 2320-2326 (2018)A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (6): 1283-1292 (2013)