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Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.

K. Lingasubramanian, A. Calimera, A. Macii, E. Macii, and M. Poncino. PATMOS, volume 6951 of Lecture Notes in Computer Science, page 214-225. Springer, (2011)

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Alberto Moreira

Alberto Coda

Alberto Ricco

Alberto Moreira

Alberto Fierro

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Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.A. Sathanur, A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino. DATE, page 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)A novel architecture for power maskable arithmetic units.L. Benini, A. Macii, E. Macii, E. Omerbegovic, M. Poncino, and F. Pro. ACM Great Lakes Symposium on VLSI, page 136-140. ACM, (2003)Energy-efficient data scrambling on memory-processor interfaces.L. Benini, A. Galati, A. Macii, E. Macii, and M. Poncino. ISLPED, page 26-29. ACM, (2003)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino. IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.K. Lingasubramanian, A. Calimera, A. Macii, E. Macii, and M. Poncino. PATMOS, volume 6951 of Lecture Notes in Computer Science, page 214-225. Springer, (2011)Low-power embedded systems.A. Macii. J. Embed. Comput., 1 (3): 303-304 (2005)Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.E. Macii, L. Bolzani, A. Calimera, A. Macii, and M. Poncino. DSD, page 298-303. IEEE Computer Society, (2008)Regression-Based Macromodeling for Delay Estimation of Behavioral Components.A. Macii, E. Macii, G. Odasso, M. Poncino, and R. Scarsi. Great Lakes Symposium on VLSI, page 188-191. IEEE Computer Society, (1999)Optimal sleep transistor synthesis under timing and area constraints.A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, and M. Poncino. ACM Great Lakes Symposium on VLSI, page 177-182. ACM, (2008)Enhanced clustered voltage scaling for low power.M. Donno, L. Macchiarulo, A. Macii, E. Macii, and M. Poncino. ACM Great Lakes Symposium on VLSI, page 18-23. ACM, (2002)

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Disambiguation of "Macii, Alberto"

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Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.

Please choose a person to relate this publication to

Alberto Moreira

Alberto Coda

Alberto Ricco

Alberto Moreira

Alberto Fierro

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Macii, Alberto"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.

Please choose a person to relate this publication to

Alberto Moreira

Alberto Coda

Alberto Ricco

Alberto Moreira

Alberto Fierro

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.