Author of the publication

Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks.

, , , , , , and . ICLR (Poster), OpenReview.net, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

PACT: Parameterized Clipping Activation for Quantized Neural Networks., , , , , and . CoRR, (2018)Exploiting approximate computing for deep learning acceleration., , , , and . DATE, page 821-826. IEEE, (2018)Ultra-Low Precision 4-bit Training of Deep Neural Networks., , , , , , , , , and . NeurIPS, (2020)FracTrain: Fractionally Squeezing Bit Savings Both Temporally and Spatially for Efficient DNN Training., , , , , , , and . NeurIPS, (2020)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel., , , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2019)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training., , , , , , , , , and 1 other author(s). NeurIPS, (2020)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , and 44 other author(s). ISCA, page 153-166. IEEE, (2021)Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators., , , and . ISPASS, page 240-242. IEEE, (2021)