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Ultra-Low Precision 4-bit Training of Deep Neural Networks.

X. Sun, N. Wang, C. Chen, J. Ni, A. Agrawal, X. Cui, S. Venkataramani, K. Maghraoui, V. Srinivasan, and K. Gopalakrishnan. NeurIPS, (2020)

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Wang Wang

Linfang Wang

Investigation of the functions of 53BP1 in DNA demethylationL. Wang. Uni Marburg, (2009)

Hao Wang

Hanchun Wang

Lei Wang

Other publications of authors with the same name

A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer.N. Sturcken, E. O'Sullivan, N. Wang, P. Herget, B. Webb, L. Romankiw, M. Petracca, R. Davies, R. Jr., G. Decad and 5 other author(s). IEEE J. Solid State Circuits, 48 (1): 244-254 (2013)COMQ: A Backpropagation-Free Algorithm for Post-Training Quantization.A. Zhang, Z. Yang, N. Wang, Y. Qin, J. Xin, X. Li, and P. Yin. CoRR, (2024)Deep Compression of Pre-trained Transformer Models.N. Wang, C. Liu, S. Venkataramani, S. Sen, C. Chen, K. Maghraoui, V. Srinivasan, and L. Chang. NeurIPS, (2022)Ultra-Low Precision 4-bit Training of Deep Neural Networks.X. Sun, N. Wang, C. Chen, J. Ni, A. Agrawal, X. Cui, S. Venkataramani, K. Maghraoui, V. Srinivasan, and K. Gopalakrishnan. NeurIPS, (2020)An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors.K. Tien, N. Sturcken, N. Wang, J. Nah, B. Dang, E. O'Sullivan, P. Andry, M. Petracca, L. Carloni, W. Gallagher and 1 other author(s). VLSIC, page 192-. IEEE, (2015)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Hybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networks.X. Sun, J. Choi, C. Chen, N. Wang, S. Venkataramani, V. Srinivasan, X. Cui, W. Zhang, and K. Gopalakrishnan. NeurIPS, page 4901-4910. (2019)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference.A. Agrawal, B. Fleischer, S. Mueller, X. Sun, N. Wang, J. Choi, and K. Gopalakrishnan. ARITH, page 92-95. IEEE, (2019)A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm2.N. Sturcken, E. O'Sullivan, N. Wang, P. Herget, B. Webb, L. Romankiw, M. Petracca, R. Davies, R. Jr., G. Decad and 5 other author(s). ISSCC, page 400-402. IEEE, (2012)

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Disambiguation of "Wang, Naigang"

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Ultra-Low Precision 4-bit Training of Deep Neural Networks.

Please choose a person to relate this publication to

Wang Wang

Linfang Wang

Hao Wang

Hanchun Wang

Lei Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Naigang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultra-Low Precision 4-bit Training of Deep Neural Networks.

Please choose a person to relate this publication to

Wang Wang

Linfang Wang

Hao Wang

Hanchun Wang

Lei Wang

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Ultra-Low Precision 4-bit Training of Deep Neural Networks.