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Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion., , and . MBMV, page 1-8. VDE/IEEE, (2021)Polynomial Formal Verification of Complex Multipliers., and . MBMV, page 1-4. VDE/IEEE, (2022)A Fast Optimal Robust Path Delay Fault Testable Adder., , , and . ED&TC, page 491-499. IEEE Computer Society, (1996)FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing., , , and . DATE, page 1-2. IEEE, (2023)Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization., , , , and . DATE, page 1110-1115. IEEE, (2021)System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations., , and . ASP-DAC, page 761-766. ACM, (2021)SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library., , , and . DSD, page 769-776. IEEE, (2022)The SyReC hardware description language: Enabling scalable synthesis of reversible circuits., and . MWSCAS, page 1063-1066. IEEE, (2013)LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing., , , , , , and . ISVLSI, page 1-6. IEEE, (2023)A compact and efficient SAT encoding for quantum circuits., , and . AFRICON, page 1-6. IEEE, (2013)