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Disambiguation of "Chang, Soon-Jyh"

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Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique.

, , and . Asian Test Symposium, page 57-62. IEEE Computer Society, (2009)

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Soon-Nan Chang

Il-Soon Chang

Chang-Soon Park

Nithya Soonthornpanich

Sukanya Soonagahalli Lava

 

Other publications of authors with the same name

An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator., , , , and . VLSI-DAT, page 1-4. IEEE, (2017)An area- and power-efficient half-rate clock and data recovery circuit., , , , , and . ISCAS, page 2129-2132. IEEE, (2014)A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window., , , and . ISCAS, page 1-4. IEEE, (2018)A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling., , , , , , , , , and 3 other author(s). ASP-DAC, page 17-18. IEEE, (2016)Histogram Based Testing Strategy for ADC., , and . ATS, page 51-54. IEEE, (2006)A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration., and . ISCAS, page 1-5. IEEE, (2021)A Physically Unclonable Function Embedded in a SAR ADC., and . ITC-Asia, page 85-89. IEEE, (2022)A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters., , and . Asian Test Symposium, page 52-57. IEEE Computer Society, (2004)A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator., , and . VLSI-DAT, page 1-4. IEEE, (2020)Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator., , , , and . ISCAS, page 1-4. IEEE, (2024)