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Formal Verification of Arithmetic Circuits by Function Extraction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2131-2142 (2016)Verification of arithmetic datapath designs using word-level approach - A case study., , and . ISCAS, page 1862-1865. IEEE, (2015)Logic Debugging of Arithmetic Circuits., , , , and . ISVLSI, page 113-118. IEEE Computer Society, (2015)Innovations for digital inclusion: Leveraging next generation networks for human development from the bottom of the pyramid.. Kaleidoscope, page 1-8. IEEE, (2009)Arithmetic Bit-Level Verification Using Network Flow Model., , and . Haifa Verification Conference, volume 8244 of Lecture Notes in Computer Science, page 327-343. Springer, (2013)Function Extraction from Arithmetic Bit-Level Circuits., , , and . ISVLSI, page 356-361. IEEE Computer Society, (2014)Verification of gate-level arithmetic circuits by function extraction., , , , and . DAC, page 52:1-52:6. ACM, (2015)Towards a research framework for a human development-based "bottom of the pyramid" ICT development strategy in South Africa., and . ECIS, page 1223-1234. (2009)Next generation ICT policy in South Africa: Towards a human development-based ICT policy., and . HCC, volume 282 of IFIP, page 109-123. Springer, (2008)A case study of programming with abstract data types in a data structures course.. SIGCSE, page 277-291. ACM, (1987)