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Disambiguation of "Ciesielski, Maciej J."

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Logic Debugging of Arithmetic Circuits.

, , , , and . ISVLSI, page 113-118. IEEE Computer Society, (2015)

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Christian Ciesielski

Mechthild Ciesielski

Thomas Ciesielski

Axel Ciesielski

Richard Ciesielski

 

Other publications of authors with the same name

Verification of arithmetic datapath designs using word-level approach - A case study., , and . ISCAS, page 1862-1865. IEEE, (2015)BDS: a BDD-based logic optimization system., , and . DAC, page 92-97. ACM, (2000)Functional Test Generation using Constraint Logic Programming., , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 375-387. Kluwer, (2001)Advanced datapath synthesis using graph isomorphism., , , and . ICCAD, page 424-429. IEEE, (2017)Layer assignment for VLSI interconnect delay minimization.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (6): 702-707 (1989)Formal Verification of Arithmetic Circuits by Function Extraction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2131-2142 (2016)Two-Dimensional Routing for the Silc Silicon Compiler.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 4 (3): 198-203 (1985)Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (10): 1647-1659 (2017)Functional Verification of Arithmetic Circuits: Survey of Formal Methods., , and . DDECS, page 94-99. IEEE, (2022)Formal Verification of Restoring Dividers made Fast and Simple., and . DAC, page 1-6. IEEE, (2023)