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25-Gbps error-free operation of chip-scale Si-photonics optical transmitter over 70°C with integrated quantum dot laser.

, , , , , , , , и . OFC, стр. 1-3. IEEE, (2016)

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Saori Hagihara

Yasuhiko Sakuma

Yasuhiko Sakuma

Yasuhiko Suzuki

 

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Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit., , , , и . ISSCC, стр. 2602-2611. IEEE, (2006)Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes., , , , , и . IEEE J. Solid State Circuits, 41 (4): 805-814 (2006)Timing optimization by replacing flip-flops to latches., , , , , и . ASP-DAC, стр. 186-191. IEEE Computer Society, (2004)Optical I/O core transmitter with high tolerance to optical feedback using quantum dot laser., , , , , , , , , и 1 other автор(ы). ECOC, стр. 1-3. IEEE, (2015)5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF., , , , , , , , , и 10 other автор(ы). OFC, стр. 1-3. IEEE, (2015)25-Gbps error-free operation of chip-scale Si-photonics optical transmitter over 70°C with integrated quantum dot laser., , , , , , , , и . OFC, стр. 1-3. IEEE, (2016)A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications., , , , , , и . IEEE J. Solid State Circuits, 41 (1): 113-121 (2006)