Author of the publication

ch error-free operation with over 300-m MMF.

K. Yashiki, Y. Suzuki, Y. Hagihara, M. Kurihara, M. Tokushima, J. Fujikata, A. Ukita, K. Takemura, T. Shimizu, D. Okamoto, J. Ushida, S. Takahashi, T. Uemura, M. Okano, J. Tsuchida, T. Nedachi, M. Fushimi, I. Ogura, J. Inasaka, and K. Kurata. OFC, page 1-3. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Saori Hagihara

Yasuhiko Suzuki

Yasuhiko Sakuma

Other publications of authors with the same name

Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit.K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura, and H. Kobatake. ISSCC, page 2602-2611. IEEE, (2006)Optical I/O core transmitter with high tolerance to optical feedback using quantum dot laser.K. Mizutani, K. Yashiki, M. Kurihara, Y. Suzuki, Y. Hagihara, N. Hatori, T. Shimizu, Y. Urino, T. Nakamura, K. Kurata and 1 other author(s). ECOC, page 1-3. IEEE, (2015)25-Gbps error-free operation of chip-scale Si-photonics optical transmitter over 70°C with integrated quantum dot laser.K. Yashiki, K. Mizutani, J. Ushida, Y. Suzuki, M. Kurihara, M. Tokushima, J. Fujikata, Y. Hagihara, and K. Kurata. OFC, page 1-3. IEEE, (2016)5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF.K. Yashiki, Y. Suzuki, Y. Hagihara, M. Kurihara, M. Tokushima, J. Fujikata, A. Ukita, K. Takemura, T. Shimizu, D. Okamoto and 10 other author(s). OFC, page 1-3. IEEE, (2015)A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications.K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake. IEEE J. Solid State Circuits, 41 (1): 113-121 (2006)Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara. IEEE J. Solid State Circuits, 41 (4): 805-814 (2006)Timing optimization by replacing flip-flops to latches.K. Yoshikawa, Y. Hagihara, K. Kanamaru, Y. Nakamura, S. Inui, and T. Yoshimura. ASP-DAC, page 186-191. IEEE Computer Society, (2004)

BibSonomy

Disambiguation of "Hagihara, Yasuhiko"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF.

Please choose a person to relate this publication to

Saori Hagihara

Yasuhiko Suzuki

Yasuhiko Sakuma

Yasuhiko Sakuma

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hagihara, Yasuhiko"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF.

Please choose a person to relate this publication to

Saori Hagihara

Yasuhiko Suzuki

Yasuhiko Sakuma

Yasuhiko Sakuma

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF.