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Disambiguation of "Vivet, Pascal"

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A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.

, , , , , , , , , , , and . ESSCIRC, page 318-321. IEEE, (2018)

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Damien Vivet

Gabriel Vivet

Pascal Maubach

Pascal Vetterlein

Pascal Häller

 

Other publications of authors with the same name

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures., , , , , and . ISVLSI, page 386-391. IEEE Computer Society, (2014)Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes., , , , , , and . 3DIC, page 1-5. IEEE, (2016)Fast and accurate power annotated simulation: Application to a many-core architecture., , , and . PATMOS, page 191-198. IEEE, (2013)3D NoC using through silicon Via: An asynchronous implementation., , , and . VLSI-SoC, page 232-237. IEEE, (2011)An Asynchronous Power Aware and Adaptive NoC Based Circuit., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization., , , , , , , and . ISLPED, page 121-126. ACM, (2020)A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs., , , , , , , , and . ESSCIRC, page 138-141. IEEE, (2008)Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools., , and . DATE, page 1715-1724. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC., , , , , , and . DATE, page 1740-1745. IEEE, (2020)