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Special Section on Advanced Technologies in Digital LSIs and Memories.. IEICE Trans. Electron., 91-C (4): 399 (2008)Code scheduling on a superscalar processor: SARCH., , , and . Syst. Comput. Jpn., 26 (9): 13-22 (1995)SNDR sensitivity analysis for cascaded ΣΔ modulators., , , , , , , , , and 7 other author(s). ISCAS, IEEE, (2000)Roundtable: Envisioning the Future for Multiprocessor SoC., , , , , , , and . IEEE Des. Test Comput., 24 (2): 174-183 (2007)14-bit 2.2-MS/s sigma-delta ADC's., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 35 (7): 968-976 (2000)Unconstrained Speculative Execution with Predicated State Buffering., , , and . ISCA, page 126-137. ACM, (1995)Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine., , , , , and . ICCD, page 106-113. IEEE Computer Society, (1993)Software pipelining with path selection., , , and . Syst. Comput. Jpn., 29 (9): 74-86 (1998)Performance Comparison of ILP Machines with Cycle Time Evaluation., , , and . ISCA, page 213-224. ACM, (1996)