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Scaling power/ground solvers on multi-core with memory bandwidth awareness.

, and . ACM Great Lakes Symposium on VLSI, page 21-26. ACM, (2010)

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Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding., , , and . Integr., (2019)Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1844-1857 (2019)Leakage power optimization for clock network using dual-Vth technology., , and . ISCAS, page 2769-2772. IEEE, (2008)SIAR: splitting-graph-based interactive analog router., , , and . ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2011)A novel fine-grain track routing approach for routability and crosstalk optimization., , , , , and . ISQED, page 621-626. IEEE, (2011)A new splitting graph construction algorithm for SIAR router., , , and . ASICON, page 1-4. IEEE, (2013)Evaluating a bounded slice-line grid assignment in O(nlogn) time., , , , , , and . ISCAS (4), page 708-711. IEEE, (2003)SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography., , and . ISQED, page 566-571. IEEE, (2013)McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs., , , , , and . ICCAD, page 1-9. IEEE, (2021)Logic and Layout Aware Voltage Island Generation for Low Power Design., , , and . ASP-DAC, page 666-671. IEEE Computer Society, (2007)