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Measurement of high-speed ADCs., и . CICC, стр. 1-7. IEEE, (2017)Spatially-Varying Image Warping: Evaluations and VLSI Implementations., , , , , , и . VLSI-SoC (Selected Papers), том 418 из IFIP Advances in Information and Communication Technology, стр. 64-87. Springer, (2012)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , и 2 other автор(ы). ESSCIRC, стр. 183-186. IEEE, (2017)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 476-478. IEEE, (2019)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , и 1 other автор(ы). ESSCIRC, стр. 115-118. IEEE, (2017)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , и 3 other автор(ы). ISCAS, стр. 1-5. IEEE, (2018)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , и 6 other автор(ы). A-SSCC, стр. 239-240. IEEE, (2019)28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 474-475. IEEE, (2017)29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 482-483. IEEE, (2017)A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS., , , , , , , , , и . ISSCC, стр. 104-106. IEEE, (2018)