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Disambiguation of "Balankutty, Ajay"

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Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging.

, , , , , , , , , , , , , , , , , , , , , , and . CICC, page 1-8. IEEE, (2024)

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Ajay Chavan

Godwin Olu Ajayi

Ajay Wakhloo

Ajay Moza

Oluyede Ajayi

 

Other publications of authors with the same name

A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS., , , , , , , , and . ISSCC, page 102-104. IEEE, (2018)Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging., , , , , , , , , and 13 other author(s). CICC, page 1-8. IEEE, (2024)A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications., , , and . IEEE J. Solid State Circuits, 45 (3): 538-553 (2010)A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications., , , and . ISSCC, page 366-367. IEEE, (2008)Mismatch Characterization of Ring Oscillators., , , and . CICC, page 515-518. IEEE, (2007)8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 126-128. IEEE, (2021)A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS., , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2015)56G/112G Link Foundations Standards, Link Budgets & Models., , and . CICC, page 1-95. IEEE, (2019)8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package., , , , , , , , , and 4 other author(s). ISSCC, page 144-146. IEEE, (2020)