Author of the publication

Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs.

, and . DAC, page 925-930. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Multi-layer floorplanning for reliable system-on-package., , , and . ISCAS (5), page 69-72. IEEE, (2004)Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling., , and . DAC, page 28:1-28:6. ACM, (2014)Profile-Driven Instruction Mapping for Dataflow Architectures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 3017-3025 (2006)DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning., , , and . ISPD, page 141-148. ACM, (2023)On Legalization of Die Bonding Bumps and Pads for 3D ICs., , , , and . ISPD, page 62-70. ACM, (2023)Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs., , , , and . ISPD, page 39-46. ACM, (2021)Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 410-423 (2022)Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs., , , , , , , and . ISLPED, page 1-6. IEEE, (2021)RTL-to-GDS Design Tools for Monolithic 3D ICs., , , , , , , , , and . ICCAD, page 126:1-126:8. IEEE, (2020)Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs., , , , and . ICCAD, page 4:1-4:9. IEEE, (2020)