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Disambiguation of "Gürkaynak, Frank K."

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MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping.

, , , , , and . ESSCIRC, page 61-64. IEEE, (2013)

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Erdal Gürkaynak

Ethem Yalç Gürkaynak

Frank K Peter

Frank K Wilhelm-Mauch

Aman K K Bhasin

 

Other publications of authors with the same name

Variable delay ripple carry adder with carry chain interrupt detection., , , and . ISCAS (5), page 113-116. IEEE, (2003)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets., , , and . CoRR, (2018)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets., , , and . IEEE Trans. Computers, 68 (4): 484-497 (2019)Automatic multiview synthesis - Towards a mobile system on a chip., , , , and . VCIP, page 1-4. IEEE, (2015)XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs., , , , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2020)Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC., , , , and . FMGALS@MEMOCODE, volume 146 of Electronic Notes in Theoretical Computer Science, page 133-149. Elsevier, (2005)Higher radix Kogge-Stone parallel prefix adder architectures., , , and . ISCAS, page 609-612. IEEE, (2000)A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic., , and . VLSI Design, 11 (2): 115-128 (2000)High speed ASIC implementations of leakage-resilient cryptography., , , , , and . DATE, page 1259-1264. IEEE, (2018)A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range., , , , , and . ESSCIRC, page 263-266. IEEE, (2021)