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Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling., , , , , , и . DAC, стр. 884-889. ACM, (2008)Variation-aware subthreshold logic circuit design., , , , , и . ASICON, стр. 1-4. IEEE, (2013)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 488-617. IEEE, (2007)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 326-606. IEEE, (2007)On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect., , , , и . ESSCIRC, стр. 258-261. IEEE, (2008)A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response., , , , и . CICC, стр. 1-2. IEEE, (2023)An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit., , , , и . MWSCAS, стр. 285-288. IEEE, (2020)A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure., , , , , и . CICC, стр. 1-4. IEEE, (2013)60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations., , , , , и . ESSCIRC, стр. 317-320. IEEE, (2012)A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance., , , , и . ESSCIRC, стр. 513-516. IEEE, (2022)