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Disambiguation of "Nambiar, Vishnu P."

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0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron.

, , , , , , , , , , and . A-SSCC, page 1-4. IEEE, (2020)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Raghu Nambiar

Sandeep Nambiar

Smitha Vishnu

Vishnu Kotrajaras

Vishnu Bendre

 

Other publications of authors with the same name

Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing., , , , and . SoCC, page 27-32. IEEE, (2019)Accelerating the AES encryption function in OpenSSL for embedded systems., , and . Int. J. Inf. Commun. Technol., 2 (1/2): 83-93 (2009)Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm., , , and . ISCAS, page 1-5. IEEE, (2019)3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications., , , , and . ISCAS, page 1-5. IEEE, (2024)Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers., , , , and . SoCC, page 242-247. IEEE, (2019)Exploring Error Correction Circuits on RISC-V based Systems for Space Applications., , , and . ISCAS, page 1-5. IEEE, (2024)A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS., , , , , , and . ISCAS, page 2433-2437. IEEE, (2022)A real-time near infrared image acquisition system based on image quality assessment., , , and . J. Real-Time Image Processing, 13 (1): 103-120 (2017)Co-simulation methodology for improved design and verification of hardware neural networks., , and . IECON, page 2226-2231. IEEE, (2013)Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)