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Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms.

, , and . ACM Trans. Design Autom. Electr. Syst., 24 (3): 32:1-32:26 (2019)

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A reconfigurable real-time SDRAM controller for mixed time-criticality systems., , , and . CODES+ISSS, page 2:1-2:10. IEEE, (2013)Deadlock Prevention in the Æthereal Protocol., , , , , and . CHARME, volume 3725 of Lecture Notes in Computer Science, page 345-348. Springer, (2005)Hybrid Timeslot Design for IEEE 802.15.4 TSCH to Support Heterogeneous WSNs., , , and . PIMRC, page 1-7. IEEE, (2018)Component-Level ASIL Decomposition for Automotive Architectures., , and . DSN Workshops, page 62-69. IEEE, (2019)A distributed architecture to check global properties for post-silicon debug., , and . European Test Symposium, page 182-187. IEEE Computer Society, (2010)A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control., , , , and . CODES+ISSS, page 130-135. ACM, (2006)Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling., , , and . IEEE Trans. Computers, 65 (6): 1882-1895 (2016)An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 4-17 (2005)An Experimental Study of Cross-Technology Interference in In-Vehicle Wireless Sensor Networks., , , and . MSWiM, page 195-204. ACM, (2016)Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC., , and . J. Syst. Archit., 61 (9): 435-448 (2015)