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A nonvolatile look-up table using ReRAM for reconfigurable logic.

W. Lin, S. Sheu, C. Kuo, P. Tseng, M. Chang, K. Su, C. Lin, K. Tsai, S. Lee, S. Liu, Y. Chen, H. Lee, C. Hsu, F. Chen, T. Ku, M. Tsai, and M. Kao. A-SSCC, page 133-136. IEEE, (2014)

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Sheu-Sheu Tan

Ming-Shye Sheu

Huey-jen Sheu

Ching-Long Sheu

Sien-Yi Sheu

Other publications of authors with the same name

A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer.M. Hong, Y. Chang, Y. Hsin, L. Liu, K. Chen, Y. Su, G. Chen, S. Yang, I. Wang, S. Rahaman and 11 other author(s). VLSI Technology and Circuits, page 379-380. IEEE, (2022)A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices.P. Wu, J. Su, Y. Chung, L. Hong, J. Ren, F. Chang, Y. Wu, H. Chen, C. Lin, H. Hsiao and 10 other author(s). ISSCC, page 1-3. IEEE, (2022)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.M. Chang, C. Lin, A. Lee, C. Kuo, G. Yang, H. Tsai, T. Chen, S. Sheu, P. Tseng, H. Lee and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.C. Chang, M. Wu, J. Lin, C. Li, V. Parmar, H. Lee, J. Wei, S. Sheu, M. Suri, T. Chang and 1 other author(s). DAC, page 30. ACM, (2019)U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.M. Wu, M. Hong, C. Shih, Y. Chang, Y. Hsin, S. Chiu, K. Chen, Y. Su, C. Wang, S. Yang and 11 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device.Y. Guo, T. Chang, C. Lin, B. Chiou, C. Lai, S. Sheu, W. Lo, and S. Chang. ISCAS, page 1-5. IEEE, (2024)A nonvolatile look-up table using ReRAM for reconfigurable logic.W. Lin, S. Sheu, C. Kuo, P. Tseng, M. Chang, K. Su, C. Lin, K. Tsai, S. Lee, S. Liu and 7 other author(s). A-SSCC, page 133-136. IEEE, (2014)RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications.A. Lee, M. Chang, C. Lin, C. Chen, M. Ho, C. Kuo, P. Tseng, S. Sheu, and T. Ku. VLSIC, page 76-. IEEE, (2015)

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Disambiguation of "Sheu, Shyh-Shyuan"

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A nonvolatile look-up table using ReRAM for reconfigurable logic.

Please choose a person to relate this publication to

Sheu-Sheu Tan

Ming-Shye Sheu

Huey-jen Sheu

Ching-Long Sheu

Sien-Yi Sheu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sheu, Shyh-Shyuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A nonvolatile look-up table using ReRAM for reconfigurable logic.

Please choose a person to relate this publication to

Sheu-Sheu Tan

Ming-Shye Sheu

Huey-jen Sheu

Ching-Long Sheu

Sien-Yi Sheu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A nonvolatile look-up table using ReRAM for reconfigurable logic.