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19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC., , , , , , , and . ISSCC, page 324-325. IEEE, (2016)A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 50 (4): 856-866 (2015)F1: High-speed interleaved ADCs., , , and . ISSCC, page 1-2. IEEE, (2015)F4: Emerging short-reach and high-density interconnect solutions for internet of everything., , , , , and . ISSCC, page 502-505. IEEE, (2016)A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS., , , , , , and . VLSIC, page 1-2. IEEE, (2014)8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 148-149. IEEE, (2014)10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS., , , , , , , , , and 9 other author(s). ISSCC, page 186-187. IEEE, (2016)A fully integrated SONET OC-48 transceiver in standard CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 36 (12): 1964-1973 (2001)Session 7 overview: Optical transceivers and silicon photonics., and . ISSCC, page 114-115. IEEE, (2013)A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio., , , , , , and . IEEE J. Solid State Circuits, 35 (12): 1820-1828 (2000)