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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Z. Zhang, X. Shen, Y. Li, G. Li, N. Qi, J. Liu, N. Wu, L. Liu, Y. Chen, and Z. Zhang. APCCAS, page 556-559. IEEE, (2022)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche ChromatographieJ. Wu. Uni Erlangen-Nürnberg, (2009)

Dagang Wu

Weijia Wu

Zongmin Wu

Hongzhong Wu

Other publications of authors with the same name

A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver.H. Wang, G. Shou, and N. Wu. ISCAS, page 3912-3915. IEEE, (2007)A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution.Y. Lin, R. Li, W. He, X. Zhou, J. He, P. Li, Y. Jiang, L. Liu, N. Wu, and C. Shi. ICTA, page 63-64. IEEE, (2020)A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology.T. Fang, M. Liu, L. Liu, Z. Cai, R. Dou, P. Feng, N. Qi, Z. Zhang, J. Liu, and N. Wu. ICTA, page 259-260. IEEE, (2021)Floorplanning and Power/Ground Network Design for A Programmable Vision Chip.H. Xu, S. Wei, N. Qi, P. Wu, J. Liu, N. Wu, L. Liu, and S. Yu. ICTA, page 184-185. IEEE, (2022)A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.Z. Zhang, Z. Zhang, Y. Chen, G. Wang, X. Shen, N. Qi, G. Li, S. Yu, J. Liu, N. Wu and 1 other author(s). ESSCIRC, page 177-180. IEEE, (2023)An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.L. Chen, C. Shi, J. He, J. Yu, H. Wang, J. Lu, L. Liu, N. Wu, and M. Tian. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4249-4259 (November 2023)A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique.Z. Zhang, L. Liu, P. Feng, and N. Wu. IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 929-941 (2017)A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.Z. Zhang, X. Shen, Z. Zhang, G. Li, N. Qi, J. Liu, Y. Chen, N. Wu, and L. Liu. ISSCC, page 86-87. IEEE, (2023)A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.Y. Li, S. Chen, Y. Yang, Q. Ma, M. Zhong, Z. Lin, L. Li, G. Li, Z. Zhang, L. Liu and 5 other author(s). APCCAS, page 360-363. IEEE, (2022)A novel architecture of local memory for programmable SIMD vision chip.Z. Chen, J. Yang, C. Shi, and N. Wu. ASICON, page 1-4. IEEE, (2013)

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Disambiguation of "Wu, Nanjian"

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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Please choose a person to relate this publication to

Jinglan Wu

Dagang Wu

Weijia Wu

Zongmin Wu

Hongzhong Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, Nanjian"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Please choose a person to relate this publication to

Jinglan Wu

Dagang Wu

Weijia Wu

Zongmin Wu

Hongzhong Wu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.