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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Z. Zhang, X. Shen, Y. Li, G. Li, N. Qi, J. Liu, N. Wu, L. Liu, Y. Chen, and Z. Zhang. APCCAS, page 556-559. IEEE, (2022)

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Li Li

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A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation.X. Shen, Z. Zhang, Y. Chen, Y. Li, Y. Zhang, G. Li, N. Qi, J. Liu, N. Wu, and L. Liu. CICC, page 1-2. IEEE, (2024)A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.Z. Zhang, Z. Zhang, Y. Chen, G. Wang, X. Shen, N. Qi, G. Li, S. Yu, J. Liu, N. Wu and 1 other author(s). ESSCIRC, page 177-180. IEEE, (2023)A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.Z. Zhang, X. Shen, Z. Zhang, G. Li, N. Qi, J. Liu, Y. Chen, N. Wu, and L. Liu. ISSCC, page 86-87. IEEE, (2023)A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.Y. Li, S. Chen, Y. Yang, Q. Ma, M. Zhong, Z. Lin, L. Li, G. Li, Z. Zhang, L. Liu and 5 other author(s). APCCAS, page 360-363. IEEE, (2022)A 400-Gb/s 64-QAM Optical Receiver with Monolithically Integrated TIA and Balanced-PD in 45-nm SOI CMOS.Y. Xiong, Y. Yang, Q. Ma, Y. Ren, L. Li, G. Li, J. Liu, Y. Li, B. Wang, N. Qi and 1 other author(s). ICTA, page 186-187. IEEE, (2023)A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers.H. Liu, G. Li, J. Liu, N. Wu, L. Liu, Y. Li, and N. Qi. ICTA, page 257-258. IEEE, (2021)A $4 112-Gb/s$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.H. Liu, N. Qi, D. Lu, Z. Dong, Z. Zhang, J. He, G. Li, L. Li, Y. Liu, Z. Dang and 6 other author(s). A-SSCC, page 1-3. IEEE, (2023)A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects.M. You, M. Chen, Y. Li, G. Li, J. Liu, Y. Chen, Y. Li, and N. Qi. ICTA, page 253-254. IEEE, (2021)A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O.Y. Yang, M. Zhong, Q. Ma, Z. Lin, L. Li, G. Li, L. Liu, J. Liu, N. Wu, H. Jia and 2 other author(s). ICTA, page 1-2. IEEE, (2022)A 2λ×100 Gb/s Optical Receiver with Si-Photonic Micro-Ring Resonator and Photo-Detector for DWDM Optical-IO.S. Chen, J. Xue, Y. Chen, Y. Gu, H. Yin, S. Bao, G. Li, B. Wang, and N. Qi. CICC, page 1-2. IEEE, (2024)

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Disambiguation of "Li, Guike"

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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Please choose a person to relate this publication to

Li Li

Li Li

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Li, Guike"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Please choose a person to relate this publication to

Li Li

Li Li

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.