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Disambiguation of "Hoang, Trong-Thuc"

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A hybrid adaptive CORDIC in 65nm SOTB CMOS process.

, , , , and . ISCAS, page 2158-2161. IEEE, (2016)

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Phan Trong Hoang

Lequy Thuc

Trong Hung Quang

Trong-Phat-Le

Nguyên Thuc Nhu

 

Other publications of authors with the same name

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation., , , , and . CoRR, (2018)High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium., , , and . IEEE Access, (2024)FPGA-based frequent items counting using matrix of equality comparators., , , , , , and . MWSCAS, page 285-288. IEEE, (2017)ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3., , , , , , and . ISOCC, page 17-18. IEEE, (2021)A hybrid adaptive CORDIC in 65nm SOTB CMOS process., , , , and . ISCAS, page 2158-2161. IEEE, (2016)Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems., , , , and . ISCAS, page 1-5. IEEE, (2024)An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode., , , , and . ISCAS, page 1-5. IEEE, (2024)FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V., , , , and . RIVF, page 31-36. IEEE, (2023)A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse., , , , , , , and . IEEE Access, (2021)Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks., , , , and . ACM Great Lakes Symposium on VLSI, page 439-442. ACM, (2023)