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Disambiguation of "sun Seo, Jae"

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Low-power neuromorphic speech recognition engine with coarse-grain sparsity.

, , , , , , and . ASP-DAC, page 111-114. IEEE, (2017)

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Sun-Aea Seo

Sun-Jae Lee

Sun-Jae Song

Jae-Sun Kim

Jae Sun Gross-Lee

 

Other publications of authors with the same name

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing., , , and . ESSCIRC, page 131-134. IEEE, (2019)Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain., , , , , , , , , and 5 other author(s). CoRR, (2018)3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression., , , , , , , , , and 1 other author(s). A-SSCC, page 1-3. IEEE, (2023)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , and . ISSCC, page 400-401. IEEE, (2013)Towards a Wearable Cough Detector Based on Neural Networks., , , , , , , , , and 3 other author(s). ICASSP, page 2161-2165. IEEE, (2018)Ranking the parameters of deep neural networks using the fisher information., , , , and . ICASSP, page 2647-2651. IEEE, (2016)Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks., , , , , , , and . FPGA, page 16-25. ACM, (2016)Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks., , , and . FPGA, page 45-54. ACM, (2017)Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 6-27 (2018)XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning., , , , , and . DATE, page 48-51. IEEE, (2022)