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A low latency and low power dynamic Carry Save Adder., , , , , , , и . ISCAS (2), стр. 477-480. IEEE, (2004)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , и 1 other автор(ы). CICC, стр. 1-4. IEEE, (2011)Performance and power evaluation of an in-line accelerator., , , , , и . Conf. Computing Frontiers, стр. 81-82. ACM, (2010)IBM second-generation RISC machine organization., , , , , , , , , и 3 other автор(ы). ICCD, стр. 138-142. IEEE, (1989)Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure., , , , , и . ICASSP, стр. 2770-2774. IEEE, (2013)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , и . ISSCC, стр. 400-401. IEEE, (2013)Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor., , , , , , и . HPCA, стр. 423-432. IEEE Computer Society, (2012)Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems., , , , и . VLSI Design, стр. 89-93. IEEE Computer Society, (2006)VICTORIA: VMX indirect compute technology oriented towards in-line acceleration., , и . Conf. Computing Frontiers, стр. 303-312. ACM, (2006)1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing., , , и . IEEE J. Solid State Circuits, 49 (4): 896-907 (2014)