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A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup., , , , , , , , , and 3 other author(s). ISSCC, page 144-146. IEEE, (2022)A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 57 (3): 688-697 (2022)A novel 10-Bit high-throughput two-stage TDC with reduced power and improved linearity., , and . ICEAC, page 50-54. IEEE, (2013)Modeling the response of Bang-Bang digital PLLs to phase error perturbations., , , , , , and . CICC, page 1-4. IEEE, (2012)A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS., , , , , , , , , and 1 other author(s). CICC, page 1-2. IEEE, (2021)O'clock: lock the clock via clock-gating for SoC IP protection., , , , , , and . DAC, page 775-780. ACM, (2022)A novel digital loop filter architecture for bang-bang ADPLL., , , , , , , and . SoCC, page 45-50. IEEE, (2012)A novel digital loop filter architecture for bang-bang ADPLL., , , , , , , and . SoCC, page 45-50. IEEE, (2012)A novel power gated digitally controlled oscillator., , and . ICEAC, page 1-4. IEEE, (2011)