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Correlating defect level to final test fault coverage for modular structured designs microcontroller family.

, , , , and . VTS, page 192-196. IEEE Computer Society, (1994)

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CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology., , , and . DAC, page 597-600. ACM, (1988)What we know after twelve years developing and deploying test data analytics solutions., , and . ITC, page 1-8. IEEE, (2016)Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling., , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)Facilitating Rapid First Silicon Debug., , and . ITC, page 628-637. IEEE Computer Society, (2002)Modeling Test Escape Rate as a Function of Multiple Coverages., , and . ITC, page 1-9. IEEE Computer Society, (2008)The roles of controllability and observability in design for test., , , and . VTS, page 211-216. IEEE Computer Society, (1992)Test Generation and Design for Test for a Large Multiprocessing DSP., , , and . ITC, page 149-156. IEEE Computer Society, (1995)The stuck-at fault: it ain't over 'til it's over.. ITC, page 1165. IEEE Computer Society, (1998)Early prediction of NBTI effects using RTL source code analysis., , , and . DAC, page 808-813. ACM, (2012)Adaptive test flow for mixed-signal/RF circuits using learned information from device under test., , and . ITC, page 674-683. IEEE Computer Society, (2010)