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Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores., , , and . IEEE Comput. Archit. Lett., 16 (1): 56-59 (2017)P-OPT: Practical Optimal Cache Replacement for Graph Analytics., , , and . HPCA, page 668-681. IEEE, (2021)BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches., , und . ISCA, Seite 198-210. ACM, (2015)Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions., und . HPCA, Seite 191-200. IEEE Computer Society, (2005)RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks., , , , , , und . DAC, Seite 7:1-7:6. ACM, (2017)In-Line Interrupt Handling for Software-Managed TLBs., und . ICCD, Seite 62-67. IEEE Computer Society, (2001)IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations., , , , , und . MICRO, Seite 1163-1177. ACM, (2023)MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker., , und . CoRR, (2024)Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing., , , , , , , , , und 2 andere Autor(en). ACM Trans. Comput. Syst., (2023)Adaptive insertion policies for high performance caching., , , , und . ISCA, Seite 381-391. ACM, (2007)