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Reconciling Selective Logging and Hardware Persistent Memory Transaction.

, , , , , , and . HPCA, page 664-676. IEEE, (2023)

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Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory., , , and . CoRR, (2020)Single-level integrity and confidentiality protection for distributed shared memory multiprocessors., , , , and . HPCA, page 161-172. IEEE Computer Society, (2008)Correlation Prefetching with a User-Level Memory Thread., , and . IEEE Trans. Parallel Distributed Syst., 14 (6): 563-580 (2003)SecureME: a hardware-software approach to full system security., , , and . ICS, page 108-119. ACM, (2011)Write-Aware Management of NVM-based Memory Extensions., , and . ICS, page 9:1-9:12. ACM, (2016)Analyzing Secure Memory Architecture for GPUs., , , and . ISPASS, page 59-69. IEEE, (2021)Improving Cost, Performance, and Security of Memory Encryption and Authentication., , , , and . ISCA, page 179-190. IEEE Computer Society, (2006)Hardware Support for Durable Atomic Instructions for Persistent Parallel Programming., , , and . DAC, page 1-6. IEEE, (2023)SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels., , and . DAC, page 973-978. IEEE, (2021)CHOP: Adaptive filter-based DRAM caching for CMP server platforms., , , , , , , , and . HPCA, page 1-12. IEEE Computer Society, (2010)