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Leveraging 3D Technology for Improved Reliability., and . MICRO, page 223-235. IEEE Computer Society, (2007)CHOP: Adaptive filter-based DRAM caching for CMP server platforms., , , , , , , , and . HPCA, page 1-12. IEEE Computer Society, (2010)Leveraging Mixed Process Three-Dimensional Die Stacking Technology for Cache Hierarchies and Reliability.. University of Utah, USA, (2009)A case for guarded power gating for multi-core processors., , , and . HPCA, page 291-300. IEEE Computer Society, (2011)Power-efficient, reliable microprocessor architectures: modeling and design methods., , , , , , , , , and 5 other author(s). ACM Great Lakes Symposium on VLSI, page 299-304. ACM, (2010)Guarded Power Gating in a Multi-core Setting., , , and . ISCA Workshops, volume 6161 of Lecture Notes in Computer Science, page 198-210. Springer, (2010)Scalable and reliable communication for hardware transactional memory., , , , and . PACT, page 144-154. ACM, (2008)Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy., , , , , , , and . HPCA, page 262-274. IEEE Computer Society, (2009)A Research Retrospective on AMD's Exascale Computing Journey., , , , , , , , , and 61 other author(s). ISCA, page 81:1-81:14. ACM, (2023)