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Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori.

, , , , and . IPDPS, IEEE, (2006)

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Fault-Tolerant Vertical Link Design for Effective 3D Stacking., , , , and . IEEE Comput. Archit. Lett., 10 (2): 41-44 (2011)Network-on-Chip virtualization in Chip-Multiprocessor Systems., , , and . J. Syst. Archit., 58 (3-4): 126-139 (2012)Silicon-aware distributed switch architecture for on-chip networks., , , , and . J. Syst. Archit., 59 (7): 505-515 (2013)Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms., , and . DATE, page 1-6. IEEE, (2023)GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal., , , and . ISC Workshops, volume 13999 of Lecture Notes in Computer Science, page 593-604. Springer, (2023)Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip., , , and . NOCS, page 169-176. IEEE Computer Society, (2012)Understanding cache hierarchy interactions with a program-driven simulator., , , and . WCAE, page 30-35. ACM, (2007)Yield-oriented evaluation methodology of network-on-chip routing implementations., , , , , , , , and . SoC, page 100-105. IEEE, (2009)CASS Introduction., , and . IPDPS Workshops, page 779-780. IEEE, (2013)A Lightweight Network of IDs to Quickly Deliver Simple Control Messages., and . Euro-Par Workshops, volume 8374 of Lecture Notes in Computer Science, page 477-487. Springer, (2013)