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Disambiguation of "Fujiwara, Hideo"

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A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings.

, , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., and . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., and . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design., , and . IEICE Trans. Inf. Syst., 94-D (7): 1430-1439 (2011)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , and . DISC, volume 5805 of Lecture Notes in Computer Science, page 172-173. Springer, (2009)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , and . WDAG, volume 1320 of Lecture Notes in Computer Science, page 290-304. Springer, (1997)A Test Generation Method Based on k-Cycle Testing for Finite State Machines., , and . IOLTS, page 232-235. IEEE, (2019)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)