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High resolution and frame rate image signal processor array design for 3-D imager.

C. Cheng, H. Hsieh, T. Fan, W. Tang, C. Liu, and P. Huang. ISPACS, page 735-739. IEEE, (2012)

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Shelley Ching-yu Hsieh

Roxana Ching-Fan Hsieh Pung

Wilhelm Ching

Paisal Chingduang

Linda Hsien

Other publications of authors with the same name

Low power and high performance 3-D multimedia platform.P. Huang, C. Lin, H. Hsieh, H. Lin, and S. Tung. Hot Chips Symposium, page 1-3. IEEE, (2012)High resolution and frame rate image signal processor array design for 3-D imager.C. Cheng, H. Hsieh, T. Fan, W. Tang, C. Liu, and P. Huang. ISPACS, page 735-739. IEEE, (2012)Low power design and dynamic power management system for VLIW DSP subsystem.H. Hsieh, S. Wen, C. Liao, H. Lin, P. Huang, and S. Tung. ISPACS, page 1-5. IEEE, (2011)Low power 3-D stacking multimedia platform with reconfigurable memory architecture.P. Huang, H. Lin, H. Hsieh, C. Lin, S. Wen, and Y. Sun. ACM Great Lakes Symposium on VLSI, page 311-312. ACM, (2013)System-level design exploration for 3-D stacked memory architectures.C. Lin, W. Hsieh, H. Hsieh, C. Liu, and J. Yeh. CODES+ISSS, page 389-390. ACM, (2011)A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.H. Hsieh, S. Lin, C. Liu, J. Yeh, S. Tung, and D. Kwai. VLSI-DAT, page 1-4. IEEE, (2013)Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC.H. Hsieh, P. Huang, C. Lin, and H. Lin. SoCC, page 317-321. IEEE, (2012)3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system.H. Hsieh, Y. Sun, J. Yeh, and P. Huang. ICASSP, page 5012-5016. IEEE, (2014)Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement.Y. Sun, C. Liu, T. Chen, H. Hsieh, J. Yeh, and Y. Chang. HPCC-ICESS, page 1618-1623. IEEE Computer Society, (2012)

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Disambiguation of "Hsieh, Hsien-Ching"

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High resolution and frame rate image signal processor array design for 3-D imager.

Please choose a person to relate this publication to

Shelley Ching-yu Hsieh

Roxana Ching-Fan Hsieh Pung

Wilhelm Ching

Paisal Chingduang

Linda Hsien

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hsieh, Hsien-Ching"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High resolution and frame rate image signal processor array design for 3-D imager.

Please choose a person to relate this publication to

Shelley Ching-yu Hsieh

Roxana Ching-Fan Hsieh Pung

Wilhelm Ching

Paisal Chingduang

Linda Hsien

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

High resolution and frame rate image signal processor array design for 3-D imager.