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3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system.

, , , and . ICASSP, page 5012-5016. IEEE, (2014)

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High resolution and frame rate image signal processor array design for 3-D imager., , , , , and . ISPACS, page 735-739. IEEE, (2012)Low power design and dynamic power management system for VLIW DSP subsystem., , , , , and . ISPACS, page 1-5. IEEE, (2011)Low power and high performance 3-D multimedia platform., , , , and . Hot Chips Symposium, page 1-3. IEEE, (2012)Low power 3-D stacking multimedia platform with reconfigurable memory architecture., , , , , and . ACM Great Lakes Symposium on VLSI, page 311-312. ACM, (2013)A case study: 3-D stacked memory system architecture exploration by ESL virtual platform., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC., , , and . SoCC, page 317-321. IEEE, (2012)System-level design exploration for 3-D stacked memory architectures., , , , and . CODES+ISSS, page 389-390. ACM, (2011)3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system., , , and . ICASSP, page 5012-5016. IEEE, (2014)Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement., , , , , and . HPCC-ICESS, page 1618-1623. IEEE Computer Society, (2012)