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Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 123-128. ACM, (2018)

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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions., , , , , , , and . DAC, page 1-6. IEEE, (2020)A Hybrid GPU + FPGA System Design for Autonomous Driving Cars., , , , , , , , , and 1 other author(s). SiPS, page 121-126. IEEE, (2019)HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation., , , , and . CoRR, (2022)HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation., , , , , and . ASP-DAC, page 140-146. IEEE, (2022)Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 123-128. ACM, (2018)FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations., , , , , and . FPGA, page 171-182. ACM, (2021)High-performance video content recognition with long-term recurrent convolutional network for FPGA., , , , , , , , and . FPL, page 1-4. IEEE, (2017)FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations., , , , , and . CoRR, (2020)WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs., , , , and . ASAP, page 258-265. IEEE, (2021)