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Disambiguation of "Chong, Kwen-Siong"

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A low-power dual-rail inputs write method for bit-interleaved memory cells.

, , , and . ISCAS, page 325-328. IEEE, (2011)

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Vanessa Chong

Sung-Won Chong-Schachel

Keum Sun Chong

Wachira Chongburee

Christopher Chong

 

Other publications of authors with the same name

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design., , , , , , , and . ISCAS, page 1-5. IEEE, (2019)High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC., , , , , and . APCCAS, page 161-164. IEEE, (2020)Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process., , , , , , and . ISCAS, page 5-8. IEEE, (2016)Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic., , , , and . ISCAS, page 492-495. IEEE, (2012)An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations., , , , , , and . ISCAS, page 2256-2260. IEEE, (2022)Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices., , , , , , , , , and 1 other author(s). Sensors, 22 (23): 9160 (2022)A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids., , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (9): 853-857 (2006)Interceptive side channel attack on AES-128 wireless communications for IoT applications., , , and . APCCAS, page 650-653. IEEE, (2016)A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline., , , , and . ISCAS, page 2589-2592. IEEE, (2015)