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A low-power dual-rail inputs write method for bit-interleaved memory cells.

, , , and . ISCAS, page 325-328. IEEE, (2011)

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High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits., , , , , and . ISCAS, page 1762-1765. IEEE, (2016)Designing globally-asynchronous-locally-system from multi-rate Simulink model., and . NEWCAS, page 1-4. IEEE, (2013)An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks., , , and . IEEE J. Solid State Circuits, 48 (2): 573-586 (2013)Non-profiling based Correlation Optimization Deep Learning Analysis., , , , , , , and . ISCAS, page 2246-2250. IEEE, (2022)Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU., , , and . ISCAS, page 353-356. IEEE, (2013)Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis., , , , , and . CoRR, (2022)Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips., , , and . APCCAS, page 5-8. IEEE, (2014)A Performance Comparison on Asynchronous Matched-delay Templates., , and . ISCAS, page 1008-1011. IEEE, (2009)A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers., , , and . ISCAS (4), page 504-507. IEEE, (2003)A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter., , and . ISCAS (5), page 381-384. IEEE, (2003)