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Disambiguation of "Gerstlauer, Andreas"

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Virtual-Link: A Scalable Multi-Producer Multi-Consumer Message Queue Architecture for Cross-Core Communication.

, , , , and . IPDPS, page 182-191. IEEE, (2021)

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Johannes Gerstlauer

Achim Gerstlauer

Ulrich Gerstlauer

Carmen Gerstlauer

Michael Gerstlauer

 

Other publications of authors with the same name

Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference., and . CoRR, (2021)Report on the 2021 Embedded Systems Week (ESWEEK)., and . IEEE Des. Test, 39 (1): 94-96 (2022)Sampling-based binary-level cross-platform performance estimation., , , , and . DATE, page 1709-1714. IEEE, (2017)Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation., and . ACM Trans. Embed. Comput. Syst., 13 (5s): 166:1-166:26 (2014)Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (2): 299-312 (2017)Guest Editorial: Special Issue on the 2015 International Conference on Embedded Computer Systems---Architectures, Modeling and Simulation (SAMOS XV), and . International Journal of Parallel Programming, (Mar 27, 2017)Virtual-Link: A Scalable Multi-Producer Multi-Consumer Message Queue Architecture for Cross-Core Communication., , , , and . IPDPS, page 182-191. IEEE, (2021)MAFAT: Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference., and . IESS, volume 669 of IFIP Advances in Information and Communication Technology, page 78-88. Springer, (2022)RTOS scheduling in transaction level models., , and . CODES+ISSS, page 31-36. ACM, (2003)Statistical Pattern Based Modeling of GPU Memory Access Streams., , , , and . DAC, page 81:1-81:6. ACM, (2017)