Author of the publication

A wideband CMOS variable-gain low noise amplifier with novel attenuator.

, , , and . ASICON, page 1-4. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A high-speed, programmable, CSD coefficient FIR filter., , and . IEEE Trans. Consumer Electronics, 48 (4): 834-837 (2002)A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique., , , , and . CICC, page 53-56. IEEE, (2009)A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit., , and . ISCAS, page 448-451. IEEE, (2008)Author's Response., , , , and . IEEE J. Solid State Circuits, 43 (9): 2170 (2008)A wideband CMOS variable-gain low noise amplifier with novel attenuator., , , and . ASICON, page 1-4. IEEE, (2013)A high PSR SOI current-mode bandgap reference., , and . ASICON, page 1-4. IEEE, (2015)A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners., , , and . ISSCC, page 358-359. IEEE, (2013)PDK design of 0.13um SOI process., , and . ASICON, page 1-4. IEEE, (2015)A broadband power detector with temperature and process compensation., , , and . ASICON, page 722-725. IEEE, (2017)Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2148-2152 (2016)