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Disambiguation of "Purohit, Sohan"

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A C++-embedded Domain-Specific Language for programming the MORA soft processor array.

, , , and . ASAP, page 141-148. IEEE Computer Society, (2010)

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Preeti Purohit

Sohan Singh

Ali Sohani

Purv Purohit

Manish Purohit

 

Other publications of authors with the same name

A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model., , , and . FPL, page 534-538. IEEE, (2009)Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems., , , and . AHS, page 113-120. IEEE Computer Society, (2010)Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor., , , and . ERSA, page 195-201. CSREA Press, (2009)Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths., , and . AHS, page 59-65. IEEE Computer Society, (2010)Design of self correcting radiation hardened digital circuits using decoupled ground bus., , and . ACM Great Lakes Symposium on VLSI, page 405-408. ACM, (2010)A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic., , and . ACM Great Lakes Symposium on VLSI, page 433-436. ACM, (2009)An area efficient design methodology for SEU tolerant digital circuits., , and . ISCAS, page 981-984. IEEE, (2010)Power/throughput/area efficient PIM-based reconfigurable array for parallel processing., , , and . SoCC, page 375-378. IEEE, (2008)Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath., , , , and . VLSI Design, page 45-50. IEEE Computer Society, (2009)MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor., , , and . AHS, page 389-396. IEEE Computer Society, (2009)