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Implementation of the 65nm Cell Broadband Engine.

M. Riley, B. Flachs, S. Dhong, G. Gervais, S. Weitzel, M. Wang, D. Boerstler, M. Bolliger, J. Keaty, J. Pille, R. Berry, O. Takahashi, Y. Nishino, and T. Uchino. CICC, page 717-720. IEEE, (2007)

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Pille Urbas

Frank Pille

Ruth Pille

Wolfgang Pille

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A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.J. Pille, D. Wendel, O. Wagner, R. Sautter, W. Penth, T. Fröhnel, S. Büttner, O. Torreiter, M. Eckert, J. Paredes and 3 other author(s). ISSCC, page 344-345. IEEE, (2010)The vector fixed point unit of the synergistic processor element of the cell architecture processor.N. Mäding, J. Leenstra, J. Pille, R. Sautter, S. Büttner, S. Ehrenreich, and W. Haller. DATE Designers' Forum, page 244-248. European Design and Automation Association, Leuven, Belgium, (2006)Implementation of the 65nm Cell Broadband Engine.M. Riley, B. Flachs, S. Dhong, G. Gervais, S. Weitzel, M. Wang, D. Boerstler, M. Bolliger, J. Keaty, J. Pille and 4 other author(s). CICC, page 717-720. IEEE, (2007)A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.P. Salz, A. Frisch, W. Penth, J. Noack, T. Kalla, R. Sautter, M. Kugel, O. Torreiter, G. Sapp, M. Lee and 4 other author(s). ESSCIRC, page 303-307. IEEE, (2017)Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI.O. Takahashi, C. Adams, D. Ault, E. Behnen, O. Chiang, S. Cottier, P. Coulman, J. Culp, G. Gervais, M. Gray and 15 other author(s). ISSCC, page 86-87. IEEE, (2008)Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, F. Kono, D. Nelson, O. Takahashi, S. Tokito, O. Torreiter and 2 other author(s). ISSCC, page 322-606. IEEE, (2007)IBM POWER8 circuit design and energy optimization.V. Zyuban, J. Friedrich, D. Dreps, J. Pille, D. Plass, P. Restle, Z. Deniz, M. Ziegler, S. Chu, M. Islam and 13 other author(s). IBM J. Res. Dev., (2015)The vector fixed point unit of the synergistic processor element of the cell architecture processor.N. Mäding, J. Leenstra, J. Pille, R. Sautter, S. Büttner, S. Ehrenreich, and W. Haller. ESSCIRC, page 203-206. IEEE, (2005)

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Disambiguation of "Pille, Jürgen"

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Implementation of the 65nm Cell Broadband Engine.

Please choose a person to relate this publication to

Pille Urbas

Frank Pille

Frank Pille

Ruth Pille

Wolfgang Pille

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pille, Jürgen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Implementation of the 65nm Cell Broadband Engine.

Please choose a person to relate this publication to

Pille Urbas

Frank Pille

Frank Pille

Ruth Pille

Wolfgang Pille

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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Chicago
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Implementation of the 65nm Cell Broadband Engine.