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Disambiguation of "Deniz, Zeynep Toprak"

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Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.

, , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 217-240. Springer, (2006)

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Ufuk Toprak

Hanefi Toprak

Cengiz Deniz

Vedat Deniz

Abdülkerim Deniz

 

Other publications of authors with the same name

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation., , and . IEEE J. Solid State Circuits, 42 (7): 1593-1606 (2007)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)Root cause identification of an hard-to-find on-chip power supply coupling fail., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2012)The POWER8TM processor: Designed for big data, analytics, and cloud environments., , , , , , , , , and 10 other author(s). ICICDT, page 1-4. IEEE, (2014)Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration., , , , , , , , , and 1 other author(s). CICC, page 1-8. IEEE, (2024)Low-power current mode logic for improved DPA-resistance in embedded systems., and . ISCAS (2), page 1059-1062. IEEE, (2005)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS., , , , and . CICC, page 1-4. IEEE, (2019)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 217-240. Springer, (2006)A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology., , , , and . APCCAS, page 21-24. IEEE, (2008)