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A multi-task-oriented security processing architecture with powerful extensibility.

, , , and . ASP-DAC, page 133-134. IEEE, (2009)

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A multi-task-oriented security processing architecture with powerful extensibility., , , and . ASP-DAC, page 133-134. IEEE, (2009)A 60mW baseband SoC for CMMB receiver., , , , and . ASP-DAC, page 479-480. IEEE, (2012)A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS., , , , , and . ASP-DAC, page 565-566. IEEE, (2012)An efficient multi-rate LDPC-CC decoder with layered decoding algorithm., , , and . ICC, page 5548-5552. IEEE, (2013)Quarter LCU based integer motion estimation algorithm for HEVC., , , and . ICIP, page 2018-2021. IEEE, (2016)Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 1089-1093 (2020)A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding., , , and . IEICE Trans. Electron., 100-C (6): 643-654 (2017)Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications., , , , and . ASICON, page 465-468. IEEE, (2011)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)