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A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture., , , and . ISCAS, page 1-5. IEEE, (2019)A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder., , , and . VLSI-SoC, page 434-439. IEEE, (2011)Parallelized Contour Based Depth Map Coding in DIBR., , , , , , and . PCM (1), volume 11164 of Lecture Notes in Computer Science, page 643-653. Springer, (2018)A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture., , , , and . ICIP, page 4168-4172. IEEE, (2018)A fast 8×8 IDCT algorithm for HEVC., , , and . ASICON, page 1-4. IEEE, (2013)A modified high-radix scalable Montgomery multiplier., , , , and . ISCAS, IEEE, (2006)Content adaptive tiling method based on user access preference for streaming panoramic video., , , , , , and . ICCE, page 1-4. IEEE, (2018)An Automatic Task Partition Method for Multi-core System., , , , , and . ISCAS, page 1-5. IEEE, (2018)A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders., , , and . ASICON, page 1-4. IEEE, (2015)A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder., , , and . MMM, volume 7131 of Lecture Notes in Computer Science, page 563-573. Springer, (2012)