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Disambiguation of "Xue, Cheng-Xin"

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13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices.

, , , , , , , , , , , and . ISSCC, page 224-226. IEEE, (2020)

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Cheng Xue

Xue-Xin Liu

Xue Xue Zhang

Jia Xue

Min Xue

 

Other publications of authors with the same name

Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices., and . ISOCC, page 164-165. IEEE, (2019)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices., , , , , , , , , and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). ISSCC, page 245-247. IEEE, (2021)A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell., , , , , and . A-SSCC, page 127-128. IEEE, (2018)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices., , , , , , , , , and 3 other author(s). VLSI Circuits, page 166-. IEEE, (2019)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , and 2 other author(s). ISSCC, page 224-226. IEEE, (2020)