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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang, T. Hsu, Y. King, C. Lin, R. Liu, C. Hsieh, K. Tang, and M. Chang. ISSCC, page 494-496. IEEE, (2018)

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Yu-En Lu

Yu Yang

Yang Yu

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SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33rd Hot Chips Symposium - August 22-24, 2021.T. Tambe, E. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, and G. Wei. HCS, page 1-13. IEEE, (2021)EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.T. Tambe, C. Hooper, L. Pentecost, E. Yang, M. Donato, V. Sanh, A. Rush, D. Brooks, and G. Wei. CoRR, (2020)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference.T. Tambe, E. Yang, Z. Wan, Y. Deng, V. Reddi, A. Rush, D. Brooks, and G. Wei. DAC, page 1-6. IEEE, (2020)EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference.T. Tambe, C. Hooper, L. Pentecost, T. Jia, E. Yang, M. Donato, V. Sanh, P. Whatmough, A. Rush, D. Brooks and 1 other author(s). MICRO, page 830-844. ACM, (2021)9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET.T. Tambe, E. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, and G. Wei. ISSCC, page 158-160. IEEE, (2021)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.W. Khwa, J. Chen, J. Li, X. Si, E. Yang, X. Sun, R. Liu, P. Chen, Q. Li, S. Yu and 1 other author(s). ISSCC, page 496-498. IEEE, (2018)OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge.T. Jia, E. Yang, Y. Hsiao, J. Cruz, D. Brooks, G. Wei, and V. Reddi. DATE, page 909-914. IEEE, (2022)FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference.E. Yang, T. Jia, D. Brooks, and G. Wei. ASAP, page 266-273. IEEE, (2021)

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Disambiguation of "Yang, En-Yu"

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

Please choose a person to relate this publication to

Yu-En Lu

Yu Yang

Yu Yang

Yu Yang

Yang Yu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, En-Yu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

Please choose a person to relate this publication to

Yu-En Lu

Yu Yang

Yu Yang

Yu Yang

Yang Yu

Other publications of authors with the same name

Disambiguation

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.