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Disambiguation of "Yoo, Byoung-Joo"

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A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.

, , , , , , , , , , , , , , , and . ISSCC, page 114-115. IEEE, (2023)

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Joo-Hyun Yoo

Chanyeol Yoo

Angelina Yoo

Young Yoo

Haiseung Yoo

 

Other publications of authors with the same name

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology., , and . DDECS, page 55-58. IEEE Computer Society, (2014)A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques., , , , , , , , , and 6 other author(s). ISSCC, page 114-115. IEEE, (2023)13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets., , , , , , , , , and 7 other author(s). ISSCC, page 250-252. IEEE, (2024)Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface., , and . ISOCC, page 49-52. IEEE, (2012)A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links., , , , , , , , , and 14 other author(s). VLSI Technology and Circuits, page 28-29. IEEE, (2022)An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS., , , , , , , , , and 17 other author(s). VLSI Technology and Circuits, page 168-169. IEEE, (2022)6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier., , , , , , , , , and 9 other author(s). ISSCC, page 122-124. IEEE, (2020)A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture., , , , , , , and . IEEE J. Solid State Circuits, 42 (6): 1318-1327 (2007)A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs., , , , , and . ISCAS, page 754-757. IEEE, (2012)