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mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.

K. Seong, D. Park, G. Bae, H. Lee, Y. Suh, W. Oh, H. Lee, J. Kim, T. Lee, G. Mo, S. Jung, D. Choi, B. Yoo, S. Park, H. Rhew, and J. Shin. ISSCC, page 114-115. IEEE, (2023)

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Sungjune Park

Rosemary Park

Jinhyung Park

Kwan Park

Shinja Park

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22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.S. Lee, K. Seong, J. Shin, H. Kim, J. Jeong, S. Yi, J. Kim, E. Kim, S. Jung, S. Hwang and 6 other author(s). ISSCC, page 338-340. IEEE, (2020)Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.K. Chae, B. Koo, J. Oh, S. Park, J. Shin, and J. Park. ISOCC, page 140-141. IEEE, (2018)A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.J. Yoo, Y. Lee, Y. Choi, H. Park, S. Park, and C. Kim. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (6): 789-793 (2018)A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.K. Chae, J. Park, J. Song, B. Koo, J. Oh, S. Yi, W. Lee, D. Kim, T. Yeo, K. Kang and 8 other author(s). ISSCC, page 406-407. IEEE, (2023)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.K. Chae, J. Choi, H. Lee, J. Choi, S. Yi, Y. Nam, S. Hwang, J. Lee, W. Lee, K. Seong and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology.K. Chae, J. Choi, S. Yi, W. Lee, S. Joo, H. Kim, H. Yi, Y. Nam, J. Choi, S. Park and 1 other author(s). ESSCIRC, page 461-464. IEEE, (2016)23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller.S. Lee, J. Oh, J. Choi, S. Ko, D. Kim, K. Koo, J. Choi, Y. Nam, S. Park, H. Lee and 7 other author(s). ISSCC, page 398-399. IEEE, (2017)A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.K. Chae, J. Song, Y. Choi, J. Park, B. Koo, J. Oh, S. Yi, W. Lee, D. Kim, K. Kang and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 231-242 (January 2024)A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL.J. Lee, Y. Jo, W. Yu, W. Kim, M. Choi, S. Park, and J. Shin. CICC, page 1-2. IEEE, (2023)A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.K. Seong, D. Park, G. Bae, H. Lee, Y. Suh, W. Oh, H. Lee, J. Kim, T. Lee, G. Mo and 6 other author(s). ISSCC, page 114-115. IEEE, (2023)

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Disambiguation of "Park, Sanghune"

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A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.

Please choose a person to relate this publication to

Sungjune Park

Rosemary Park

Jinhyung Park

Kwan Park

Shinja Park

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Park, Sanghune"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.

Please choose a person to relate this publication to

Sungjune Park

Rosemary Park

Jinhyung Park

Kwan Park

Shinja Park

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.